Data storage device and method for flash block management

ABSTRACT

The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a plurality of flash memory areas and a controller. Each of the flash memory areas comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, selects a target memory area to which the target data is to be written from the flash memory areas, sets a physical address range parameter according to the target memory area, sets a spare block pool parameter according to the target memory area, and writes the target data to a current data block of the target memory area.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of pending application Ser. No.13/474,801, filed on May 18, 2012, the entirety of which is incorporatedby reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to flash memories, and more particularly tomanagement of blocks of flash memories.

2. Description of the Related Art

A flash memory is a non-volatile computer storage chip that can beelectrically erased and reprogrammed A flash memory is primarily used inmemory cards, USB flash drives, solid-state drives, and similarproducts, for general storage and transfer of data. Example devices forapplications of a flash memory include personal computers, PDAs, digitalaudio players, digital cameras, mobile phones, video games, and so on.In addition to being non-volatile, flash memory offers fast read accesstimes, as fast as dynamic RAM, although not as fast as static RAM orROM. A flash memory now costs far less than byte-programmable EEPROM andhas become the dominant memory type for when a significant amount ofnon-volatile, solid state storage is needed. Thus, a method forappropriately managing a flash memory is required to improve theperformance of the flash memory.

BRIEF SUMMARY OF THE INVENTION

The invention provides a data storage device. In one embodiment, thedata storage device is coupled to a host, and comprises a plurality offlash memory areas and a controller. Each of the flash memory areascomprises a spare block pool and a data block pool, wherein the spareblock pool comprises a plurality of spare blocks, and the data blockpool comprises a plurality of data blocks. The controller receivestarget data from the host, selects a target memory area to which thetarget data is to be written from the flash memory areas, sets aphysical address range parameter according to the target memory area,sets a spare block pool parameter according to the target memory area,and writes the target data to a current data block of the target memoryarea.

The invention also provides a method for flash block management. In oneembodiment, a data storage device is coupled to a host and comprises aplurality of flash memory areas and a controller, each of the flashmemory areas comprises a spare block pool and a data block pool, thespare block pool comprises a plurality of spare blocks, and the datablock pool comprises a plurality of data blocks. First, target data isreceived from the host. A target memory area to which the target data isto be written is selected by the controller from the flash memory areas.A physical address range parameter is then set according to the targetmemory area by the controller. A spare block pool parameter is then setaccording to the target memory area by the controller. Finally, thetarget data is written to a current data block of the target memory areaby the controller.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 is a block diagram of a data storage device according to theinvention;

FIG. 2 is a flowchart of a method for managing blocks of a flash memoryaccording to the invention;

FIG. 3 is a schematic diagram of a current data block of a flash memoryaccording to the invention;

FIG. 4 is a flowchart of a method for getting spare blocks from a datablock pool according to the invention;

FIG. 5 is a schematic diagram of calculation of a jail threshold valueand a hot threshold value according to the invention;

FIG. 6 is a schematic diagram of a data merge process according to theinvention;

FIG. 7 is a schematic diagram of a wear-leveling process according tothe invention;

FIG. 8 is a block diagram of a data storage device capable of switchingmemory areas according to the invention;

FIG. 9 is a flowchart of a method for managing blocks of a plurality offlash memory areas according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

Referring to FIG. 1, a block diagram of a data storage device 100according to the invention is shown. In one embodiment, the data storagedevice 100 comprises a controller 102 and a flash memory 104. The flashmemory 104 comprises a plurality of blocks for data storage. In oneembodiment, the flash memory 104 comprises a spare block pool 110 and adata block pool 130. The spare block pool 110 comprises a plurality ofspare blocks 111˜11 n storing invalid data. The data block pool 130comprises a plurality of blocks 131˜13 m storing data. In oneembodiment, the data storage device 100 is coupled to a host. Thecontroller must manage the blocks of the flash memory 104 according tocommands sent by the host. The flash memory 104 specifies a blockaccording to a physical address, and the host specifies a blockaccording to a logical address. The controller 102 therefore mustconvert logical addresses sent by the host to physical addresses. In oneembodiment, the controller 102 records a corresponding relationshipbetween logical addresses and physical addresses of the blocks in anaddress link table.

Each of the data blocks 131˜13 m comprises a plurality of pages. Whendata is stored in a page of a data block, the page is referred to as adata page. When a data page has a corresponding logical address, thedata page is referred to as a valid page. In one embodiment, thecontroller 102 respectively counts a total number of valid pages of eachof the data blocks 131˜13 m to obtain a valid page number, and recordsthe valid page numbers of the data blocks 131˜13 m in a valid counttable. In addition, a frequency at which a block is erased is referredto as an erase count of the block. In one embodiment, the controller 102also records the erase counts of all of the blocks of the flash memory104 in an erase count table.

Referring to FIG. 2, a flowchart of a method 200 for managing blocks ofthe flash memory 104 according to the invention is shown. When the hostsends a target data to be written to the data storage device 100, thecontroller receives the target data (step 202), and writes the targetdata to a current data block (step 204). Referring to FIG. 3, aschematic diagram of a current data block 300 of the flash memory 104according to the invention is shown. The current data block 300comprises a plurality of pages. The pages of the current data block 300may be used to store data pages corresponding to different logicaladdresses. For example, data 311 stored in page 301 may correspond to alogical address L1, data 312 stored in page 302 may correspond to alogical address L2, and data 313 stored in page 303 may correspond to alogical address L3.

After the target data is written to the current data block, thecontroller 102 then determines whether the current data block is full ofdata (step 206). In one embodiment, when controller 102 currentprogramming page is the final page of the current data block, thecontroller 102 determines that the current data block is full. Thecontroller 102 then updates a plurality of tables according to theinformation of the current data block (step 208). In one embodiment, theupdated tables comprise an address link table and a valid page counttable. Because the data stored in the pages of the current data blockrespectively corresponds to different logical addresses, the controller102 must write the mapping relationship between the physical addressesof the pages of the current data block and the logical addresses of thedata stored therein to the address link table. In addition, a page wouldbe marked as an invalid page if host cancel or new that page. Thecontroller 102 must calculate a total number of valid page in a block todetermine a valid page count of that block, and then writes the validpage count to the valid page count table. After more data cancelingand/or renewing, some data blocks in the data block pool 130 store novalid page and their valid page counts will be set to zero. Then, theseblocks which valid page count are zero will be set as spare blocks andbe get from a data block pool 130 to the spare block pool 110 (step210). The step 210 will be further illustrated in detail with FIG. 4.The controller 102 then obtains a spare block from the spare block pool110 and then assigns the spare block to be a current data block forreceiving new data sent by the host (step 212).

Referring to FIG. 5, a schematic diagram of calculation of a jailthreshold value and a hot threshold value according to the invention isshown. All blocks of the flash memory 104 has an erase count. And theerase count of a block would be add one when controller set the block asa spare block and put the block to spare block pool. A minimum erasecount of the blocks of the flash memory 104 will increase with time andthe block with the minimum erase count would change in some situation.Therefore, the controller 102 will frequently determine the minimumerase count according to changing of the erase counts of all blocks ofthe flash memory 104. After the minimum erase count is determined, thecontroller 102 then adds a first difference WL_TH1 to the minimum erasecount to obtain a hot threshold value, and adds a second differenceWL_TH2 to the minimum erase count to obtain a jail threshold value, asshown in FIG. 5. In one embodiment, the first difference WL_TH1 is lessthan the second difference WL_TH2. Here the second difference WL_TH2 isgreater than the first difference WL_TH1, and the jail threshold valueis therefore greater then the hot threshold value. When an erase countof a block is greater than the hot threshold value, the controller 102determines the block to be a hot block. When an erase count of a blockis greater than the jail threshold value, the controller 102 determinesthe block to be a jail block, and puts the jail block into the jail pool120 shown in FIG. 1. For example, the blocks 502,503, and 504 shown inFIG. 5 have erase counts greater than the jail threshold value and aretherefore put into the jail pool 120. Although the jail blocks 121˜12 kare spare blocks, when the controller 102 retrieves a new spare blockfor storing data from the spare block pool 110, the controller 102 doesnot retrieve the jail blocks. The erase count of the jail block istherefore prevented from being further increased unless the jail blockis released in the future.

Referring to FIG. 4, a flowchart of a method 400 for getting spareblocks from the data block pool 130 according to the invention is shown.The method 400 comprises the detailed steps for performing the step 210of the method 200 shown in FIG. 2. First, the controller 102 determinesa minimum erase count from the erase counts of the blocks of the flashmemory 104, and calculates a jail threshold value according to theminimum erase count. After updating the jail threshold value, some erasecounts of the jail blocks 121˜12 k in the jail pool 120 may be less thanthe updated jail threshold value. The controller 102 therefore comparesthe erase counts of the jail blocks 121˜12 k of the jail pool 120 withthe jail threshold value, and releases the jail block from the jail pool120 to the spare block pool 110 if its erase count less than the jailthreshold value (step 402).

Some of the data blocks 131˜13 m of the data block pool 130 may compriseno valid data and have a valid page count equal to zero. The controller102 therefore searches the data block pool 130 for any target block withvalid page counts equal to zero (step 404), then puts the target blocksto the spare block pool 110 and adds 1 to the erase counts of the targetblocks (step 406). The controller 102 then determines whether there isany erase count of the target block greater than the jail thresholdvalue (step 408). If yes, the controller puts the target block which hasa greater erase count than the jail threshold value to the jail pool 120(step 412). If not, the controller 102 then determines whether there isany erase count of the target block greater than the hot threshold value(step 410). If yes, the controller 102 determines the target block to bea hot block, and then adds the number of the target blocks to the hotblock count (step 414).

Refer back to FIG. 2. After the target data is written to the currentdata block (step 204), the controller 102 then determines whether thecurrent data block is full of data (step 206). If the current data blockis not full, the controller 102 determines whether the currentprogramming page is a first page of the current data block (step 214).If yes, for example, the controller is current programming the page 301shown in FIG. 3, the first page of the current data block 300, thecontroller 102 then determines whether a spare block count is less thana spare block count threshold value (step 216). The spare block countindicates a total number of the spare blocks in the spare block pool110. In one embodiment, the spare block count threshold value is 15. Andif a spare block is obtained from the spare block pool 110 and then iserased as a new current data block, the total number of the spare blocksin the spare block pool decreases one. When the spare block count isless than the spare block count threshold value (step 216), thecontroller 102 sets data move information for a data merge process toinitiate the data merge process to increase the spare block count (step218).

In one embodiment, the data move information for initiating a data mergeprocess comprises physical addresses of a plurality of source datablocks with data to be merged and a physical address of a destinationspare block to which the merged data is written. The controller 102selects data blocks with minimum valid page counts from the data blockpool 130 as the source data blocks, and obtains a spare block as thedestination spare block. Referring to FIG. 6, a schematic diagram of adata merge process according to the invention is shown. When the datamerge process begins, four source data blocks 601, 602, 603, and 604with minimum valid page counts are selected from the data block pool 130and a destination spare block 610 is selected from the spare pool. Thecontroller 102 then erases the destination spare block 610 and mergesthe valid data D1, D2, D3, and D4 of the source data blocks 601, 602,603, and 604 in RAM (not shown) to obtain merged data (D1+D2+D3+D4).Then controller 102 writes the merged data (D1+D2+D3+D4) to thedestination spare block 610. Finally, the controller 102 puts the sourcedata blocks 601, 602, 603, and 604 to the spare block pool 110, and putsthe destination spare block 610 written with the merged data(D1+D2+D3+D4) to the data block pool 130. Therefore, the total number ofthe spare blocks in the spare block pool will increase three after thedata merge process is performed.

Refer back to FIG. 2. When the current programming page is the firstpage of the current data block (step 214), and the spare block count isgreater, not less, than the spare block count threshold value (step216), the controller 102 then determines whether a hot block count isgreater than zero (step 220). The hot block count indicates a totalnumber of the hot blocks which erase counts are greater than the hotthreshold value in the spare block pool 110. Because the hot blocks havea high erase count, if the spare block poll 110 comprises a greaternumber of hot blocks, the controller 102 should retrieve a hot blockfrom the spare block pool 110 and proceed the wear-leveling process witha data block which has the least erase count in the data pool. Thus,when the spare block count is great than the threshold and the hot blockcount is greater than zero (step 220), the controller 102 sets data moveinformation for a wear-leveling process to initiate the wear-levelingprocess to decrease the hot block count (step 222).

In one embodiment, the data move information for initiating awear-leveling process comprises the physical address of at least onesource data block with data to be copied and the physical address of atleast one destination spare block to which the copied data is written.When there is a plurality of hot blocks in the spare block pool 110, thecontroller 102 determines the hot blocks to be the destination spareblocks. Because the data blocks with low erase counts store data withlow updating probability, the controller 102 selects data blocks withminimum erase counts from the data block pool 130 as the source datablocks. Referring to FIG. 7, a schematic diagram of a wear-levelingprocess according to the invention is shown. When the wear-levelingprocess begins, a source data block 701 with a minimum erase count isselected from the data block pool 130 and a destination spare block 711is selected from the spare block pool 110. The controller 102 thenerases the destination spare block 711 and writes the copied data D5 tothe destination spare block 711′. Then the source data block 701′ with alow erase count is put into the spare block pool 110, and thedestination spare block 711′ with a high erase count is put from thespare block pool 110 to the data block pool 130. The total number of thehot blocks in the spare block pool 110 therefore will decrease one afterthe wear-leveling process is performed.

Refer back to FIG. 2. When a current programming page to which thetarget data is written is not a first page of the current data block(step 214), the controller 102 determines whether the data moveinformation is set (step 224). If the data move information for a datamerge process or a wear-leveling process is set, the controller 102performs a portion of the data merge process or the wear-levelingprocess according to the data move information within a limited timeperiod (step 226). The limited time period is determined by a standardfor data transmission requirement between the host and the data storagedevice 104. For example, after the host sends a write command and thetarget data to the controller 102, the host must receive a responseinformation about execution completion of the write command within alimited time period of 100 ms˜300 ms, and the controller 102 can onlyperform a portion of the data merge process or the wear-leveling processduring the limited time period.

Due to the limited time period, the controller 102 slices the data moveoperation of the data merge process or the wear-leveling process into aplurality of partial data move operations. After a new target data iswritten to a current programming page of the current data block (step204), if the current programming page is not a first page of the currentdata block (step 214), one of the partial data move operations of thedata merge process or the wear-leveling process is performed during thelimited time period. For example, as shown in FIG. 6, when the data moveinformation of a data merge process is set (step 224), the controller102 selects a plurality of target pages with valid data from the sourcedata blocks 601, 602, 603, and 604, and copies the valid data from thetarget pages to the destination spare block 610 within the limited timeperiod. For example, as shown in FIG. 7, when the data move informationof a wear-leveling process is set (step 224), the controller 102 selectsa plurality of target pages from the source data block 701, and copiesdata from the target pages to the destination spare block 711 within thelimited time period. After a few write commands are executed, the datamove operation of the data merge process or the wear-leveling process isalso completed.

Referring to FIG. 8, a block diagram of a data storage device 800capable of switching memory areas according to the invention is shown.The data storage device 800 comprises a controller 802 and a pluralityof flash memory areas 810, 820, and 830. In one embodiment, the flashmemory areas 801, 820, and 803 are respective flash memory chips. Forexample, the flash memory area 810 is an SLC flash memory, the flashmemory area 820 is an MLC flash memory, and the flash memory area 830 isa TLC flash memory. In another embodiment, the flash memory areas arememory partitions of a single flash memory chip. Each of the flashmemory areas 810, 820, and 830 comprises a spare block pool and a datablock pool. The controller 802 independently manages the blocks of eachof the flash memory areas 810, 812, and 814. For example, the controller802 performs a data merge process or a wear-leveling process between thespare block pool and the data block pool of a single flash memory area.When block management is performed, the controller 802 does not exchangedata between the blocks of a flash memory area and another flash memoryarea.

Referring to FIG. 9, a flowchart of a method 900 for managing blocks ofthe flash memory areas 810, 820, and 830 according to the invention isshown. First, the controller 802 receives target data from a host (step902). The controller 802 then determines a target memory area to whichthe target data is written from a plurality of flash memory areas 810,820, and 830 (step 904). The controller 802 then sets a physical addressrange parameter according to the target memory area (step 906). In oneembodiment, the physical address range parameter comprises a startaddress parameter and an end address parameter, and the controller 802sets the start address parameter to be a start address of the targetmemory area, and sets the end address parameter to be an end address ofthe target memory area. The controller 802 then sets a spare block poolparameter according to the target memory area (step 908). In oneembodiment, the controller 802 records the physical addresses of thespare blocks of the spare block pool of the target memory area to thespare block pool parameter. The controller 802 then writes the targetdata to a current data block of the target memory area (step 910).

The controller 802 then performs a data merge process or a wear-levelingprocess on the blocks of the target memory area according to the steps206˜226 of the method 200 shown in FIG. 2. In other words, thecontroller 802 performs the data merge process on the blocks of the datablock pool of the target memory area (step 912), or performs thewear-leveling process between the spare blocks of the spare block poolof the target memory area and the data blocks of the data block pool ofthe target memory area (step 914). Setting of the data move informationof the data merge process of step 912 or the wear-leveling process ofstep 914 is identical to those of the steps 218 or 222, and performingof the data merge process of step 912 or the wear-leveling process ofstep 914 is also identical to that of the step 226. The controller 802can therefore independently manage the blocks of the target memory areawithout intervening block management of other flash memory areas.

While the invention has been described by way of example and in terms ofpreferred embodiment, it is to be understood that the invention is notlimited thereto. To the contrary, it is intended to cover variousmodifications and similar arrangements (as would be apparent to thoseskilled in the art). Therefore, the scope of the appended claims shouldbe accorded the broadest interpretation so as to encompass all suchmodifications and similar arrangements.

What is claimed is:
 1. A data storage device, coupled to a host,comprising: a plurality of flash memory areas, each comprising a spareblock pool and a data block pool, wherein the spare block pool comprisesa plurality of spare blocks, and the data block pool comprises aplurality of data blocks; and a controller, receiving target data fromthe host, selecting a target memory area to which the target data is tobe written from the flash memory areas, setting a physical address rangeparameter according to the target memory area, setting a spare blockpool parameter according to the target memory area, and writing thetarget data to a current data block of the target memory area.
 2. Thedata storage device as claimed in claim 1, wherein the controllerfurther performs a data merge process on the blocks of the data blockpool of the target memory area, and performs a wear-leveling processbetween the spare blocks of the spare block pool of the target memoryarea and the data blocks of the data block pool of the target memoryarea.
 3. The data storage device as claimed in claim 1, wherein thephysical address range parameter comprises a start address parameter andan end address parameter, and the controller sets the start addressparameter to be a start address of the target memory area, and sets theend address parameter to be an end address of the target memory area. 4.The data storage device as claimed in claim 1, wherein the controllerrecords the physical addresses of the spare blocks of the spare blockpool of the target memory area to the spare block pool parameter.
 5. Thedata storage device as claimed in claim 2, wherein when the controllerperforms the data merge process, the controller selects a plurality oftarget data blocks with minimum valid page counts from the data blockpool of the target memory area, selects a target spare block from thespare block pool of the target memory area, moves data stored in thetarget data blocks to the target spare block, erases the data from thetarget data blocks, puts the target spare block to the data block poolof the target memory area, and puts the target data blocks to the spareblock pool of the target memory area.
 6. The data storage device asclaimed in claim 2, wherein when the controller performs thewear-leveling process, the controller selects a plurality of target datablocks with minimum erase counts from the data blocks of the data blockpool of the target memory area, selects a plurality of target spareblocks with maximum erase counts from the spare blocks of the spareblock pool of the target memory area, moves data stored in the targetdata blocks to the target spare blocks, erases the data from the targetdata blocks, puts the target spare blocks to the data block pool of thetarget memory area, and puts the target data blocks to the spare blockpool of the target memory area.
 7. The data storage device as claimed inclaim 1, wherein the flash memory areas respectively correspond todifferent flash memory chips.
 8. The data storage device as claimed inclaim 1, wherein the flash memory areas are different memory partitionsof a single flash memory.
 9. A method for flash block management,wherein a data storage device is coupled to a host and comprises aplurality of flash memory areas and a controller, each of the flashmemory areas comprises a spare block pool and a data block pool, thespare block pool comprises a plurality of spare blocks, and the datablock pool comprises a plurality of data blocks, the method comprising:receiving target data from the host; selecting a target memory area towhich the target data is to be written by the setting a physical addressrange parameter according to the target memory area by the controller;setting a spare block pool parameter according to the target memory areaby the controller; and writing the target data to a current data blockof the target memory area by the controller.
 10. The method as claimedin claim 9, wherein the method further comprises: performing a datamerge process on the blocks of the data block pool of the target memoryarea by the controller; and performing a wear-leveling process betweenthe spare blocks of the spare block pool of the target memory area andthe data blocks of the data block pool of the target memory area by thecontroller.
 11. The method as claimed in claim 9, wherein the physicaladdress range parameter comprises a start address parameter and an endaddress parameter, and setting of the physical address range parametercomprises: setting the start address parameter to be a start address ofthe target memory area; and setting the end address parameter to be anend address of the target memory area.
 12. The method as claimed inclaim 9, wherein setting of the spare block pool parameter comprises:recording the physical addresses of the spare blocks of the spare blockpool of the target memory area to the spare block pool parameter by thecontroller.
 13. The method as claimed in claim 10, wherein performing ofthe data merge process comprises: selecting a plurality of target datablocks with minimum valid page counts from the data block pool of thetarget memory area; selecting a target spare block from the spare blockpool of the target memory area; moving data stored in the target datablocks to the target spare block; erasing the data from the target datablocks; putting the target spare block to the data block pool of thetarget memory area; and putting the target data blocks to the spareblock pool of the target memory area.
 14. The method as claimed in claim10, wherein performing of the wear-leveling process comprises: selectinga plurality of target data blocks with minimum erase counts from thedata blocks of the data block pool of the target memory area; selectinga plurality of target spare blocks with maximum erase counts from thespare blocks of the spare block pool of the target memory area; movingdata stored in the target data blocks to the target spare blocks;erasing the data from the target data blocks; putting the target spareblocks to the data block pool of the target memory area; and putting thetarget data blocks to the spare block pool of the target memory area.15. The method as claimed in claim 9, wherein the flash memory areasrespectively correspond to different flash memory chips.
 16. The methodas claimed in claim 9, wherein the flash memory areas are differentmemory partitions of a single flash memory.